Recently, single-chips have been developed using a complementary metal-oxide-semiconductor (CMOS) process and has been applied in an element array. To increase density of the element array, the CMOS process needs to be reduced by using nanoscale CMOS devices. However, how to fabricate nanoscale CMOS devices and parasitic resistances effect are problems.
U.S. Patent No. 2005/0176226 A1 discloses a method of manufacturing an electronic device comprising a bottom-gate TFT. The method comprises steps of: forming a doped amorphous silicon gate layer on a substrate with the gate layer defining a gate, forming a gate insulating layer over the gate, forming an amorphous silicon active layer over the gate insulating layer and overlying at least part of the gate and annealing the amorphous silicon active layer to form a polysilicon active layer. A thinner gate insulating layer can be used giving a TFT having a low threshold voltage. However, the electronic device has a device size that is hard to make smaller.
U.S. Patent No. 2008/0293246 A1 discloses a vertical FET structure with nanowires forming the FET channels. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance. However, the vertical FET structure requires six photomasks to be fabricated.
U.S. Patent No. 2010/0330759 discloses a method of forming a transistor comprising a transistor body, a surrounding gate insulator, a surrounding gate and an element characteristic. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. The transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. The surrounding gate insulator is formed around the semiconductor pillar, and the surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided. The element characteristic is easily affected by a complicated gate structure process.
U.S. Patent No. 2009/0065852 A1 discloses a nonvolatile memory device with a nanowire channel and a method for fabricating the same is proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side walls of the side-gate. The nonvolatile memory device with a nanowire channel and dual-gate control can thus be achieved. This nonvolatile memory device can enhance data writing and erasing efficiency, and also has a capability of low voltage operation. Moreover, through a process of low cost and easy steps, highly reproducible and mass producible fabrication of nanowire devices can be accomplished. However, the nonvolatile memory device requires an extra hard mask to form an insulating device nanowire. The side-gate is difficult to cover with a gate dielectric layer.
Accordingly, a new nanoscale CMOS device and a fabricating method are needed to overcome the foregoing problems.